1. Field of the Invention
This invention relates to integrated circuits and the manufacture thereof, and particularly to the fabrication of a low resistance base shunt for a bipolar transistor extending from a base contact into close proximity with an emitter region.
2. Description of the Prior Art
Integrated circuit designers are faced with the difficult task of fabricating circuits which operate at the highest possible speed while occupying a minimal amount of the silicon surface area. As semiconductor structures have become increasingly complex, it is difficult to fabricate all of the necessary active and passive devices within the integrated circuit in a reasonable number of process steps with a minimal number of masks, while achieving the desired performance.
One well known integrated circuit fabrication technology is the manufacture of bipolar transistors. A widely used and well known process for fabricating bipolar transistors is described in U.S. Pat. No. 3,648,125 entitled "Method of Fabricating Integrated Circuits with Oxidized Isolation and the Resulting Structure" and issued to Douglas L. Peltzer. Peltzer teaches the use of oxide isolation to provide electrically isolated pockets of epitaxial silicon in which active and/or passive devices may be fabricated. These individual devices are then interconnected by metal or polysilicon conductors deposited across the surface of the silicon. Numerous other oxide isolated bipolar processes have been developed. In almost all of these processes, it is desired to make the transistor switch as rapidly as possible. One well known restriction on the switching speed of bipolar devices is the resistance presented by the extrinsic base region, that is, for a vertical device that portion of the base extending laterally between the emitter and the base contact.
FIG. 1a is a cross-sectional view of a portion of a prior art semiconductor structure. The structure depicted is a cross-section of a vertical NPN transistor. As shown, a buried layer of strongly-doped N conductivity provides a collector region under an epitaxial silicon layer. The collector is separated from the strongly-doped emitter by a base region. An emitter contact provides an electrical connection to the emitter, while a pair of base contacts provide electrical connections to the base. The emitter contact is prevented from shorting to the base region by an annular thin oxide isolation region surrounding the emitter at the upper surface of the epitaxial layer.
FIG. 1b is a top view of the structure shown in FIG. 1a, and illustrates a significant disadvantage of the structure. In particular, the transistor structure of FIG. 1a will not switch as rapidly as desired because of the relative high resistance of the extrinsic base region. The extrinsic base region is that portion of the base extending between the emitter and the base contact. As shown in FIG. 1b, the sheet resistance A of the base contact will be on the order of 0.03 ohms per square, while the sheet resistance of the extrinsic base B will on the order of 700 ohms per square. The relatively high resistance B reduces the switching speed of the transistor.
At least two techniques have been developed for lowering the resistance of the extrinsic base. According to one technique, a plug implant is employed to extend the base downward and thereby increase the collector-base capacitance. The capacitance is increased because the base region is more strongly doped in closer proximity to the collector region.
When a polycrystalline silicon contact is employed, another prior art technique for lowering the resistance of the extrinsic base is to form a spacer oxide on the sides of the polycrystalline silicon contact, and then use the spacer oxide to mask additional implantation of the substrate with base impurity to thereby more strongly dope all of the base region except that portion beneath the emitter contact and spacer oxide.